In a Power over Data Lines (PoDL) system, DC power from Power Sourcing Equipment (PSE) is transmitted over a single twisted wire pair to a Powered Device (PD) after the system goes through a powering up routine, referred to as a detection and classification routine, that indicates that the PD is PoDL compatible. The same twisted wire pair also transmits/receives differential data signals, typically in accordance with the Ethernet protocols. A DC coupling network couples DC to the wire pair, and an AC coupling network couples the differential data to the wire pair. DC and AC decoupling networks decouple the DC power and AC data from the wire pair. In this way, the need for providing any external power source for the PD can be eliminated. The standards for PoDL are set out in IEEE 802.3 and are well-known.
In a PoDL system, the units coupled to the wire pair are sometimes referred to as a master and a slave (rather than a PSE and a PD), since either unit may control the other. The master may sometimes act as a slave. In some of the examples below, one unit is designated as a master and the other unit is designated as a slave; however, the designations may be reversed depending on the function being performed.
FIG. 1 illustrates conventional PoDL system including AC/DC coupling/decoupling networks (C1-C4, L1-L4) between a PSE 10 and a PD 12. The PSE 10 includes a DC voltage source 13 and a differential data portion whose interface to the wire pair 16 is identified as a physical layer (PHY) 17. The PHY 17 may include transceivers and other circuitry for processing the data in accordance with the IEEE standards. The PD 12 has a similar PHY 18. The details of the data portion of the PoDL system are not particularly relevant to the present invention.
Other types of systems (non-PoDL systems) include a DC power source at both end terminals, so PoDL is not required for normal operation. Data is transmitted over a twisted wire pair between the two terminals.
In some applications, it is desired for the system to enter a low power sleep mode (or standby mode) after being initially powered up, where power is removed from certain circuitry to conserve power. This may be done by a master or slave issuing a sleep mode code, using the differential data path (the twisted wire pair), and the processors in the master and slave then controlling the circuits to go into a low power mode. However, the PHYs must remain powered to receive a wake-up signal over the data path. The PHYs consume power in the sleep mode, which may be undesirable if very low power consumption is needed.
What is needed is a technique for allowing the PHYs to also be disabled in a sleep mode and allowing the PHYs to be woken up without using the data path.